Among semiconductor devices, a solid state drive (SSD) device storing information using a semiconductor device such as a flash memory unlike a hard disk drive (HDD), which is a mechanical apparatus, in spite of being operated similarly to the HDD, has become recently prominent as the next generation storage apparatus that will replace the HDD.
The SSD device has been used in order to replace the HDD used in a computer or a mini hard disk used in a mobile terminal. Since the SSD device stores data using the semiconductor device such as the flash memory, it does not generate mechanical movement as compared with the HDD, and may decrease a long search time, latency time, and mechanical delay time, which are problems of the HDD.
The SSD device generally has NAND flash memories configured in an array to implement a large storage area. The flash memories configuring the SSD device should be thoroughly tested in a manufacturing step to identify all defects in the flash memory array. In this SSD device test, a significant time is required for a data comparison test for the flash memories.
A typical method for implementing the data comparison test is to write a known pattern to the flash memory, read back contents of the flash memories, and then compare the read-back data with the written known pattern.
FIG. 1 is a schematic block diagram showing a memory device test apparatus for a general data comparison test; and FIG. 2 is a diagram showing a data flow in a data comparison test process in a system architecture of FIG. 1.
The memory device test apparatus is implemented by a host system 110 that includes a host central processing unit (CPU) 111, a main memory 112, multiple peripheral component interconnect express (PCIe) switches 113 and 114, and a host bridge 115 communicating and connecting between the host CPU 111, the main memory 112, and the PCIe switches 113 and 114. Multiple test target SSD devices (DUTs) are mounted as PCIe devices in downstream ports of the PCIe switches 113 and 114. Although the SSD devices are shown as test targets in the accompanying drawings, the present invention is not limited thereto, but may be used for a data comparison test of a memory device such as a flash memory, or the like. The respective SSD devices are connected to the PCIe switches 113 and 114 with two lanes.
An example in which two PCIe switches 113 and 114 are mounted in the host system 110 and four SSD devices (DUTs) are mounted in the PCIe switches 113 and 114, respectively, is shown in FIG. 1. Each DUT is a 2-lane PCIe device, and since a total of eight DUTs are connected to the PCIe switches, the host bridge 115 should include sixteen lanes.
A data comparison test process using the SSD test apparatus according to the related art configured as described above will be described. As described above, the data comparison test process includes a writing process, a reading-back process, and a data comparing process, and each process in a traditional processor architecture system includes the following several detailed steps.
First, the known data pattern should be copied from a storage (not shown) to the main memory or be generated by a test code. In this case, a required time is determined by a storage medium of the host system 110 (in which data are stored) and a bandwidth of the main memory 112 of the host system 110. That is, it takes a time for the host system 110 to copy the known data pattern from a hard drive or a network position into the main memory 112.
Next, in the writing process, the data pattern should be written in the SSD device (DUT). That is, the data stored in the main memory 112 are moved from the main memory 112 to the SSD device through any interface supported by the SSD device. A time required for the writing process is also determined by the bandwidth of the main memory 112 of the host system 110 and/or all interface protocols present between the main memory 112 of the host system 110 and an interface to the SSD device (DUT).
Next, in the reading-back process, when the data are recorded, the host system 110 should read back contents written in the SSD device (DUT). In the reading-back process, the data should again pass through a protocol interface between the SSD device (DUT) and the host system 110 and an interface of the main memory 112 of the host system 110. In this case, the host system 110 should store both of the known data pattern and the data read-back from the SSD device (DUT) in the main memory 112.
Next, in the comparing process, the host system 110 should compare two data chucks; the known data and the read-back data with each other. The host system 110 should read the two data chucks from the main memory 112 in order to compare the data with each other. In this case, a time cost is again required for accessing the main memory 112.
In summary, the data pattern is generated by the host CPU 111 and is stored in the main memory 112. In the writing process, the data flow from the main memory 112 to the SSD device (DUT) while crossing all bandwidth limiting paths of the host bridge 115. In the reading-back process, the data again flow from the SSD device (DUT) to the main memory 112 while crossing all the bandwidth limiting paths of the host bridge 115. In addition, these processes should be repeated for all the SSD devices (DUT) mounted in the host system. That is, in all the processes of the data comparison test, all the data for testing all the SSD devices (DUTs) should be written in the main memory or be read from the main memory.
Therefore, an entire time required for the data comparison test is mainly determined by the bandwidth of the main memory 112 of the host system 110 and the bandwidth of the protocol between the host system 110 and the SSD device (DUT). Since modern SSD devices drive a very high speed serial protocol, a very high speed memory interface is required in order to maintain a bandwidth required for testing a single SSD device.
Since a considerable part of a hardware cost in an SSD device test apparatus is a host CPU subsystem, the test apparatus generally supports a test for one or more SSD device per CPU subsystem. The system architecture provides independent high speed serial protocol interfaces for each SSD device supported by one CPU. In the case in which the CPU supports tests for multiple SSD devices, the bandwidth of the main memory of the host system always becomes a bottleneck during a data comparison test, which causes a test time bottleneck.